1. Technical Field
This disclosure relates generally to integrated circuits, and, more specifically, to implementing virtual memory systems.
2. Description of the Related Art
To maximize the size of addressable memory space, modern computer systems often implement a virtual memory system in which a portion of the addressable space corresponds to memory locations in faster primary storage (e.g., random access memory (RAM)) and the remain portion corresponds to slower, but larger secondary storage (e.g., hard drives). As data is requested, it is moved from secondary storage into primary storage, where it can be accessed more quickly. When the data is no longer needed, it is written back to secondary storage.
In order to track where data is currently located, memory requests (i.e., requests to read data or write data) are addressed to virtual addresses that are subsequently mapped (i.e., translated) to corresponding physical addresses in memory. These translations are typically performed at a memory management unit (MMU), which accesses a master table of translations in memory (called a “page table”) and stores a subset of translations in a localized buffer (called a “translation lookaside buffer (TLB)”). Accordingly, if a particular virtual address does not have a translation in the TLB (i.e., it is said to “miss” the TLB), the MMU may include a table walk unit that attempts to retrieve the translation from the page table in main memory and to load the translation into the TLB.
If the table walk unit is unable to find a translation for a particular virtual address in the page table, this generally means that the memory request is addressed to a location corresponding to secondary storage, rather than primary storage. In this event, the table walk unit notifies the operating system via a “page fault” indication. The operating system, in turn, reads the requested data from secondary storage and loads it into primary storage to make it accessible (when data is moved, it is typically moved as a block of multiple bytes called a “page”). The operating system also inserts a set of corresponding translations into the page table. As memory requests are subsequently received that are addressed to ones of these virtual addresses, a portion of these translations may eventually be loaded into the TLB by the MMU. In some instances (such as when the TLB is full), loading a new translation into the TLB may result in an older translation being evicted from the TLB.